Abstract: The testing and design for testability of chiplet-based integrated chips constitute a central challenge in this domain. Existing approaches leverage the inherent architecture of system on chips to test routers, physical interconnects, and logic cores. This paper first reviews the standards proposed by IEEE (Institute of Electrical and Electronics Engineers) for testing conventional chips as well as systems on chips. And then categorizes common fault models in chiplet-based integrated chips and introduces corresponding testing and design for testability techniques for stuck-at faults and physical interconnect faults such as open and short faults. Subsequently, it surveys relevant technologies and research on test data transmission, routing algorithms for network on chips, and test scheduling. Furthermore, it examines widelyused commercial testing tools and components for chiplet-based integrated chips, analyzing their architectural characteristics in detail. Finally, it discusses potential future directions for the development of testing and design for testability techniques in chiplet-based integrated chips.