Abstract: The testing and design for testability (DFT) of chiplet-based integrated chips constitute a central challenge in this domain. Existing approaches leverage the inherent architecture of chiplet systems to test routers, physical interconnects, and logic cores. The thesis first reviews the standards proposed by IEEE for conventional chip testing as well as chiplet-based system testing. It then categorizes common fault types in chiplet systems and introduces corresponding testing and DFT techniques for stuck-at faults and interconnect faults such as open and short defects. Subsequently, it surveys relevant technologies and research on test data transmission, network-on-chip routing algorithms, and test scheduling. Furthermore, it examines widely used commercial testing tools and industrial testing components for chiplet systems, analyzing their architectural characteristics in detail. Finally, it discusses potential future directions for the development of testing and DFT techniques in chiplet-based integrated chips.