Research on Communication Topologies for Chiplet Architecture: Progress and Challenges

Chiplet-based multi-chip integration designs provide a flexible and scalable solution that surpasses traditional system on chip monolithic integration. However, inter-Chiplet communication has become a significant bottleneck affecting overall system performance. The network on interposer plays a pivotal role in multi-chip systems, directly influencing both performance and development costs. This paper reviews the communication topologies of Chiplet-based network on interposer structures and delves into the design and implementation methods of current inter-Chiplet communication architectures. It comprehensively covers the communication process from protocol, interface, to application layers, classifying interconnect topologies based on structural configurations, and providing in-depth analyses and cross-comparisons for each category. Additionally, this paper explores the future directions of inter-Chiplet communication technologies, emphasizing technical challenges and potential solutions, and highlights the importance of workload-oriented, reusable interposer layers and topology design. This review aims to provide researchers with a comprehensive overview of the current state of network on interposer technology while simultaneously forecasting its development trends in future multi-chip integrated systems, offering systematic insights to advance frontier research in semiconductor technologies.