In this paper, four design methods of gearbox are introduced, and their timing analysis is carried out. By comparing the number of cells (area), power consumption, speed and stability, a gearbox based on roundrobin saving mode is selected and applied to 100GE physical coding sublayer circuit. It can take out the output value within a certain range, which overcomes the influence of phase difference between input and output clocks and greatly improves the speed and stability of the circuit. After structure optimization and pipeline design, the gearbox can work stability at the clock frequency of over 700 MHz and meet the design requirement. The physical coding sublayer circuit which including the gearbox has been taped out in 0.18 μm complementary metal oxide semiconductor technology and measured results show that it can work properly at speed of 100 Gb/s.