Hardware-Assisted Intra-Process Protection Technologies

As software ecosystems become highly modular and third-party codes are widely integrated, the traditional "all-equal" resource access model within a process has exposed security vulnerabilities. Relying solely on software-based security mechanisms faces inherent limitations, including performance bottlenecks, susceptibility to metadata tampering, and poor compatibility. Consequently, hardware-assisted security protection has emerged as an important development direction. This paper presents a survey of processor hardware-assisted intra-process protection technologies. It begins by examining existing mechanisms in commercial processors—namely, NX bit, CET, MPK, PAC, and MTE—and identifies common deficiencies, including the absence of an in-process trusted computing base, insufficient tag space, a lack of system call protection as well as a lack of register and instruction set partition. Subsequently, it systematically analyzes the latest academic advances and emerging trends across four research directions: pointer-level checking, compartment-based isolation, system call interception, and register partitioning, while also highlighting the limitations of current solutions. Finally, it outlines the remaining technical challenges that persist in this field.